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constant impedance k |z| spst rf switch 30 mhz to 8000 mhz f2910 datasheet ? 2016 integrated device technology, inc 1 august 30, 2016 description the f2910 is a high reliability, low insertion loss, 50 ? absor ptive spst rf switch designed for a multitude of wireless and rf applications. this device covers a broad frequency range from 30 mhz to 8000 mhz. in addition to providing low insertio n loss, the f2910 also delivers excellent linearity and isolation performance while providing a 50 ? termination on rf2 in the isolation mode. the f2910 includes a patent pending constan t impedance k | z | feature for the rf2 port. k | z | maintains near constant impedance when switching rf ports and improves h ot switching ruggedness. k | z | minimizes vswr transients and reduces phase and amplitude variations when switching. the f2910 uses a single positive supply voltage supporting e ither 3.3 v or 1.8 v control logic. competitive advantage the f2910 provides constant impedance for one rf port du ring transitions, improving a systems hot-switching ruggedness. the device also supports high power handling and high isolation. constant impedance k | z | during switching transition low insertion loss high isolation excellent linearity extended temperature range: -55 c to +105 c typical applications base station 2g, 3g, 4g portable wireless repeaters and e911 systems digital pre-distortion public safety infrastructure wimax receivers and transmitters military systems, jtrs radios rfid handheld and portable readers cable infrastructure wireless lan test / ate equipment features insertion loss 0.58 db at 2 ghz high isolation 51 db at 2 ghz high linearity iip3 of 65 dbm wide single positive supply voltage range 3.3 v and 1.8 v compatible control logic operating temperature -55 c to +105 c 2 mm x 2 mm 8-pin dfn package block diagram figure 1. block diagram
f2910 datasheet ? 2016 integrated device technology, inc 2 august 30, 2016 pin assignments figure 2. pin assignments for 2 mm x 2 mm x 0.9 mm 8-v fqfp-n C top view rf2 v1 vdd rf1 nc gnd gnd nc f2910 1 2 3 4 8 7 6 5 ep pin descriptions table 1. pin descriptions number name description 1, 4 nc this pin may be connected to the paddle and can be grounded. 2, 3 gnd ground. also, internally connected to the ground paddle. ground this pin as close to the device as possible. 5 rf1 rf1 port. matched to 50 in the insertion loss state only. if this pin is not 0 v dc, then an external coupling capacitor must be used. 6 v dd power supply. bypass to gnd with capacitors shown in th e typical application circuit as close as possible to pin. 7 v1 logic control pin. see table 6 for proper logic setting. 8 rf2 rf2 port. matched to 50 . if this pin is not 0v dc, then an external coupling ca pacitor must be used. ep exposed pad. internally connected to gnd. solder t his exposed pad to a pcb pad that uses multiple ground vias to provide heat transfer out of the devic e and into the pcb ground planes. these multiple ground vias are also required to achieve the specified r f performance.
f2910 datasheet ? 2016 integrated device technology, inc 3 august 30, 2016 absolute maximum ratings stresses beyond those listed below may cause permanent d amage to the device. functional operation of the device at these or any other conditions beyond those indicated in the operational sect ion of this specification is not implied. exposure to absolu te maximum rating conditions for extended periods may affect device reliability . table 2. absolute maximum ratings parameter symbol minimum maximum units v dd to gnd v dd - 0.3 +6.0 v v1 to gnd v logic -0.3 lower of (v dd + 0.3v, 3.6v) v rf1, rf2 to gnd v rf - 0.3 +0.3 v rf input power port 1 or 2 other port terminated into 50 ? [a] p rf12 33 dbm rf input power port 1 in isolation port 2 terminated into 50 ? [a] p rf1_iso 23 rf input power port 2 in isolation port 1 terminated into 50 ? [a] p rf2_iso 30 maximum junction temperature t jmax +140 c storage temperature range t st - 65 +150 c lead temperature (soldering, 10s) t lead +260 c electrostatic discharge C hbm (jedec/esda js-001-2012) v esdhbm 2000 (class 2) v electrostatic discharge C cdm (jedec 22-c101f) v esdcdm 1000 (class c3) v a. v dd = 2.7 v to 5.5 v, 30 mhz f rf 8000 mhz, t c = 105c, z s = z l = 50 ohms.
f2910 datasheet ? 2016 integrated device technology, inc 4 august 30, 2016 recommended operating conditions table 3. recommended operating conditions parameter symbol condition minimum typical maximum units power supply voltage v dd 2.7 5.5 v logic input high threshold v ih 2.7 v v dd 5.5 v 1.1 [a] lower of (v dd , 3.6) v logic input low threshold v il - 0.3 [b] 0.6 v operating temperature range t case exposed paddle temperature -55 +105 c rf frequency range f rf 30 8000 [c] mhz rf continuous input cw power (non-switched) [d] p rf rf1 or rf2 as the input (insertion loss state) t c = 85 oc 30 dbm t c = 105 oc 27 rf1 as the input (isolation state) t c = 85 oc 20 t c = 105 oc 17 rf2 as the input (isolation state) t c = 85 oc 27 t c = 105 oc 24 rf continuous input power (rf hot switching cw) [d] p rfsw applied to rf2 input switching between insertion loss to isolation states t c = 85 oc 24 dbm t c = 105 oc 21 rf1/2 port impedance z rfx insertion loss state 50 rf2 port impedance z rfx isolation state 50 a. items in min/max columns in bold italics are guaranteed by test. b. items in min/max columns that are not bold/italics are guaran teed by design characterization. c. to achieve best performance from 5 C 8 ghz, the use of bypass capacitors as described in the applications circuit section is required. d. levels based on: v dd = 2.7 v to 5.5 v, 30 mhz f rf 8000 mhz, z s = z l = 50 ohms. see figure 3 for power handling derating vs rf frequency. figure 3. maximum rf input operating power vs. rf frequen cy
f2910 datasheet ? 2016 integrated device technology, inc 5 august 30, 2016 electrical characteristics table 4. electrical characteristics typical application circuit: v dd = 3.3 v, t case = +25 c, f rf = 2 ghz, driven port = rf2, input power = 0 dbm, z s = z l = 50 . pcb board trace and connector losses are de-embedded unless oth erwise noted. iip2 / iip3: p in = 13 dbm / tone, 50 mhz spacing. performance beyond 5 ghz based on application circuit (figure 20) usin g best rf pcb design practices. see note c for details. parameter symbol condition min typ max units logic current i ih , i il -1 +1 a dc current i dd v dd =3.3 v 190 304 [a] a v dd =5.0 v 220 374 insertion loss il 0.03 ghz 0. 38 db 0.35 ghz 0.4 4 1.0 ghz 0. 5 0 0.70 [b] 2.0 ghz 0.55 0.80 3.0 ghz 0. 6 0 0.85 4.0 ghz 0. 6 7 0.90 5.0 ghz 0. 7 5 1.00 6.0 ghz 0. 8 0 [c] 7.0 ghz 1.0 0 [c] 8.0 ghz 1.55 [c] isolation iso 0.03 ghz 85 db 0.35 ghz 66 7 3 1.0 ghz 55 61 2.0 ghz 45 51 3.0 ghz 40 46 4.0 ghz 35 4 1 5.0 ghz 30 3 7 6.0 ghz 33 [c] 7.0 ghz 29 [c] 8.0 ghz 26 [c] max rf2 port vswr during switching vswr insertion loss to isolation 3 .3 :1 isolation to insertion loss 2 .0 :1 rf1, rf2 return loss (insertion loss state) rf rl 2.0 ghz 2 7 db 3.0 ghz 25 4.0 ghz 20 5.0 ghz 1 8 6.0 ghz 20 [c] 7.0 ghz 2 5 [c] 8.0 ghz 1 3 [c] a. items in min/max columns in bold italics are guaranteed by test. b. items in min/max columns that are not bold/italics are guaran teed by design characterization. c. to achieve performance beyond 5 ghz, the use of bypass capacitors (bom c2, c3, and c5) installed close to the device as embodied in the evaluation board per the application circuit (figure 20) is required. see the appropriate typical oper ating conditions graphs.
f2910 datasheet ? 2016 integrated device technology, inc 6 august 30, 2016 electrical characteristics (cont.) typical application circuit: v dd = 3.3 v, t case = +25 c, f rf = 2 ghz, driven port = rf2, input power = 0 dbm, z s = z l = 50 . pcb board trace and connector losses are de-embedded unless oth erwise noted. iip2 / iip3: p in = 13 dbm / tone, 50 mhz spacing. performance beyond 5 ghz based on application circuit (figure 20) usin g best rf pcb design practices. see note c for details. parameter symbol condition minimum typical maximum units rf2 return loss (isolation state) rf rlt 2.0 ghz 27 db 3.0 ghz 2 7 4.0 ghz 25 5.0 ghz 20 6.0 ghz 15 [c] 7.0 ghz 12 [c] 8.0 ghz 10 [c] input 1db compression [d] icp 1db 0.03 ghz 34 dbm 3.0 ghz 35 4.0 ghz 35 input 0.1db compression [d] icp 0.1db 0.03 ghz 33 dbm 3.0 ghz 34 4.0 ghz 34 input ip2 [e] iip2 f1 = 0.35 ghz f2 = 0.40 ghz 123 dbm f1 = 0.95 ghz f2 = 1.00 ghz 124 f1 = 2.40 ghz f2 = 2.45 ghz 118 input ip3 [e] iip3 0.03 ghz 65 dbm 0.35 ghz 65 1.0 0 ghz 68 2.4 0 ghz 67 non - rf driven spurious [f] spur max any port w hen externally terminated into 50 - 102 dbm switching time [g] t sw 50% control to 90% rf 265 500 ns 50% control to 10% rf 2 2 5 500 50% control to rf settled to within +/ - 0.1 db of insertion loss value 280 maximum switching rate sw rate 25 khz maximum video feed-through on rf ports vid ft peak transients during switching. measured with 20 ns risetime, 0 to 3.3 v control pulse rise time 25 mvpp fall time 45 a. items in min/max columns in bold italics are guaranteed by test. b. items in min/max columns that are not bold/italics are guaran teed by design characterization. c. to achieve performance beyond 5 ghz, the use of bypass capacitors (bom c2, c3, and c5) installed close to the device as embodied in the evaluation board per the application circuit (figure 20) is required. see the appropriate typical oper ating conditions graphs. d. the input 0.1 and 1 db compression point is a linearity figur e of merit. refer to absolute maximum ratings section for the maximum rf input power. e. rf1 or rf2 driven iip2 / iip3 results when in insertion los s state. ip2 frequency = f1 + f2. f. spurious due to on-chip negative voltage generator. sp urious fundamental is approximately 5.7 mhz. g. f rf = 1 ghz.
f2910 datasheet ? 2016 integrated device technology, inc 7 august 30, 2016 thermal characteristics table 5. package thermal characteristics parameter symbol value units junction to ambient thermal resistance. ja 159.5 c/w junction to case thermal resistance. (case is defined as the exposed paddle) jc 15.1 c/w moisture sensitivity rating (per j - std - 020) msl 1 typical operating conditions (toc) unless otherwise noted: v dd = 3.3 v. z l = z s = 50 ohms single ended. f rf = 2 ghz. p in = 13 dbm / tone applied to rf2 port for two tone linearit y tests. two tone frequency spacing = 50 mhz. all temperatures are referenced to the exposed paddle. evaluation kit traces and connector losses are de-embedd ed. performance beyond 5 ghz as listed in the electrical char acteristics is based on the application circuit (figure 20 ) with bypass capacitors (bom c2, c3, and c5) installed. the capacitors must be ins talled in close proximity to the device as embodied in the evaluation board with best practices followed for pcb design. performance above 5 ghz de-rated as shown in typical performance ch aracteristics plots figure 10 to figure 13 when application circuit with bypass c apacitors is not utilized. unless otherwise noted, c2, c3 and c5 are installed in f ollowing plots.
f2910 datasheet ? 2016 integrated device technology, inc 8 august 30, 2016 typical performance characteristics figure 4. insertion loss vs. frequency over temperature figure 5. isolation vs. frequency over temperature figure 6. return loss vs. frequency over temp [rf1 insertion loss state] figure 7. return loss vs. frequency over temp [rf2 insertion loss state] figure 8. return loss vs. frequency over temperature [rf2 terminated state] figure 9. evaluation board loss vs. frequency -3.5 -3.0 -2.5 -2.0 -1.5 -1.0 -0.5 0.0 0 2000 4000 6000 8000 10000 insertion loss (db) frequency (mhz) -55c 25c 105c -100 -90 -80 -70 -60 -50 -40 -30 -20 0 2000 4000 6000 8000 10000 isolation (db) frequency (mhz) -55c 25c 105c -45 -40 -35 -30 -25 -20 -15 -10 -5 0 0 2000 4000 6000 8000 10000 return loss (db) frequency (mhz) -55c 25c 105c -45 -40 -35 -30 -25 -20 -15 -10 -5 0 0 2000 4000 6000 8000 10000 return loss (db) frequency (mhz) -55c 25c 105c -35 -30 -25 -20 -15 -10 -5 0 0 2000 4000 6000 8000 10000 return loss (db) frequency (mhz) -55c 25c 105c -1 -0.9 -0.8 -0.7 -0.6 -0.5 -0.4 -0.3 -0.2 -0.1 0 0 2000 4000 6000 8000 10000 loss (db) frequency (mhz) -55c 25c 105c
f2910 datasheet ? 2016 integrated device technology, inc 9 august 30, 2016 typical performance characteristics figure 10. insertion loss vs. frequency with and without capacitors figure 11. isolation vs. frequency with and without capacitors figure 12. return loss vs. frequency with and without capacitors figure 13. return loss vs. frequency with and without capacitors [state 0] figure 14. input ip3 vs. frequency figure 15. 1 db com pression at 3 ghz -3.5 -3.0 -2.5 -2.0 -1.5 -1.0 -0.5 0.0 0 2000 4000 6000 8000 10000 insertion loss (db) frequency (mhz) w/c2, c3 and c5 installed w/c2, c3 and c5 removed -100 -90 -80 -70 -60 -50 -40 -30 -20 0 2000 4000 6000 8000 10000 isolation (db) frequency (mhz) w/c2, c3 and c5 installed w/c2, c3 and c5 removed -40 -35 -30 -25 -20 -15 -10 -5 0 2000 4000 6000 8000 10000 return loss (db) frequency (mhz) w/c2, c3 and c5 installed w/c2, c3 and c5 removed -35 -30 -25 -20 -15 -10 -5 0 2000 4000 6000 8000 10000 return loss (db) frequency (mhz) w/c2, c3 and c5 installed w/c2, c3 and c5 removed 60 62 64 66 68 70 72 74 76 78 80 0 500 1000 1500 2000 2500 iip3 (dbm) frequency (mhz) -55c 25c 105c -2 -1.5 -1 -0.5 0 0.5 1 18 20 22 24 26 28 30 32 34 36 compression (db) input power (dbm) -55c 25c 105c
f2910 datasheet ? 2016 integrated device technology, inc 10 august 30, 2016 typical performance characteristics figure 16. switching time isolation to insertion loss figure 17. switching time insertion loss to isolation
f2910 datasheet ? 2016 integrated device technology, inc 11 august 30, 2016 evaluation kit picture figure 18. top view figure 19. bottom view
f2910 datasheet ? 2016 integrated device technology, inc 12 august 30, 2016 control mode table 6. switch control truth table v1 (logic) state port match 0 isolation rf1 port reflective, rf2 port terminated into 50 ohms 1 insertion loss rf1 and rf2 port matched to 50 ohm evaluation kit / applications circuit figure 20. electrical schematic note: the use of bypass capacitors c2, c3, and c5 as listed in the bom (table 7) is required to achieve performanc e as listed in the electrical characteristics for frequencies beyond 5 ghz. the capacitors must be installed in close proximity to the d evice as embodied in the evaluation board with best practices followed for pcb des ign.
f2910 datasheet ? 2016 integrated device technology, inc 13 august 30, 2016 table 7. bill of material (bom) part reference qty description manufacturer part # manufacturer c1 1 0.1 f 10%, 16v, x7r, ceramic capacitor (0402) grm155r71c104ka88d murata c2 1 0.5 pf 0.1 pf, 50v, c0g, ceramic capacitor (0402) gjm1555c1hr50bb01 murata c3 1 4.5 pf 0.1 pf, 50v, c0g, ceramic capacitor (0402) gjm1555c1h4r5bb01d murata c4 0 not installed (0402) c5 1 4.9 pf 0.1 pf, 50v, c0g, ceramic capacitor (0402) gjm1555c1h4r9bb01 murata r1 1 15k 1%, 1/10w, resistor (0402) erj - 2rkf1502x panasonic r2 1 18k 1%, 1/10w, resistor (0402) erj - 2rkf1802x panasonic r3, r4 2 0 1/10w, jumper (0402) erj - 2ge0r00x panasonic j1 C j4 4 sma edge mount 142 - 0761 - 881 cinch connectivity j5 1 conn header vert 4x2 pos gold 67997 - 108hlf amphenol fci tp1 0 not installed (red test point loop) tp2, tp3 0 not installed (black test point loop) u1 1 spst switch 2 mm x 2 mm 8 pin dfn f2910nbgp idt 1 printed circuit board f2910 evkit rev 01 idt
f2910 datasheet ? 2016 integrated device technology, inc 14 august 30, 2016 evaluation kit operation default start-up control pins include no internal pull-down resistors to log ic low or pull-up resistors to logic high. power supplies a common v cc power supply should be used for all pins requiring dc pow er. all supply pins should be bypassed with external capa citors to minimize noise and fast transients. supply noise can degrade noise figure and fast transients can trigger esd clamps and cause them to fail. supply voltage change or transients should have a slew r ate smaller than 1 v / 20 s. in addition, all control p ins should remain at 0 v ( 0.3 v) while the supply voltage ramps or while it return s to zero. control pin interface if control signal integrity is a concern and clean signals c annot be guaranteed due to overshoot, undershoot, r inging, etc., the following circuit at the input of each control pin is recommended. this appl ies to control pin 7 as shown in figure 21. if bypass ca pacitor c5 as described in the application circuit (figure 20) is used to achieve high f requency performance optimization, the use of an addition al 2 pf capacitor as shown in figure 21 is not necessary. figure 21. control pin signal integrity improvement circuit
f2910 datasheet ? 2016 integrated device technology, inc 15 august 30, 2016 external supply setup set up a v cc power supply in the voltage range of 2.7 v to 5.5 v w ith the power supply output disabled. logic control setup using the evkit to manually set the control logic: on connector j5, connect a 2-pin shunt from v cc (pin 3) to v logic (pin 4). this connection provides the v cc voltage supply to the eval board logic control pull-up network. resistors r1 and r2 form a voltage divider to set the v ih level over the 2.7 v to 5.5 v v cc range for manual logic control. connector j5 has one logic input pin: v1 (pin 5). see ta ble 6 for logic truth table. with the pull-up network ena bled (as noted above) this pin can be left open to provide a logic high through pull- up resistor r1. to set a logic low for v1, connect a 2-pin shunt on j5 from v ctl (pin 5) to gnd (pin 6). note that when using the on board r1/r2 voltage divider , the current draw from the v cc supply will be higher by approximately v cc / 33 k?. using external control logic: pins 3, 4, 6, 7, and 8 of j5 should have no external connections. external logic control is applied to j5 v1 (p in 5). see table 5 for the logic truth table. turn on procedure setup the supplies and evkit as noted in the external su pply setup and logic control setup sections above. enable the v cc supply. set the desired logic setting to achieve the desired table 5 configuration. note that external control logic should not be applied without v cc being present. turn off procedure set the logic control to a logic low. disable the v cc supply.
f2910 datasheet ? 2016 integrated device technology, inc 16 august 30, 2016 package drawings figure 22. package outline drawing
f2910 datasheet ? 2016 integrated device technology, inc 17 august 30, 2016 recommended land pattern figure 23. recommended land pattern
f2910 datasheet ? 2016 integrated device technology, inc 18 august 30, 2016 ordering information orderable part number package msl rating shipping packaging temperature f2910nbgp 2 x 2 x 0.9 mm 8 - vfqfp - n msl1 bulk - 55 to +105 c F2910NBGP8 2 x 2 x 0.9 mm 8 - vfqfp - n msl1 tape and reel - 55 to +105 c f2910evbi evaluation board marking diagram 1. line 1 is the part number. 2. line 2 C 6 is last digit of the year. 3. line 2 C u is the workweek code 4. line 2 C ag is the sequential code
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